1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with reduced contact resistance and improved performance.
2. Discussion of the Related Art
FIGS. 1A to 1D are cross-sectional views showing process steps of a conventional method for fabricating a semiconductor device.
Referring initially to FIG. 1A, a plurality of field oxide layers 12 are formed on the surface of a semiconductor substrate 11 with a local oxidation of silicon (LOCOS) process. A buffer oxide layer 13 is grown on active regions which are defined by the field oxide layers 12, and a polysilicon layer is then formed on the entire surface of the semiconductor substrate 11 including the field oxide layers 12. Subsequently, a photoresist film (not shown) is coated on the polysilicon layer and patterned by an exposure and development process. Next, using the photoresist pattern as a mask, the polysilicon layer is selectively patterned to form gate electrodes 14. Thereafter, an insulating layer is formed on the entire surface of the semiconductor substrate 11 including the gate electrodes 14 and then is etched back to form sidewall spacers 15 on both sides of each of the gate electrodes 14. A high-temperature low-pressure dielectric (HLD) layer 16 is deposited on the entire surface of the semiconductor substrate 11 including the gate electrodes 14. The HLD layer 16 is then selectively removed with an etching process to expose a portion of the semiconductor substrate 11 (with the buffer oxide layer 13 o thereon) and the gate electrode 14.
Referring to FIG. 1B, a Titanium (Ti) layer 17 is formed on the entire surface including the semiconductor substrate 11 and the gate electrodes 14.
Then, an annealing process is executed to form a silicide layer 17a on the gate electrode 14 and on the semiconductor substrate 11 at both sides of the gate electrode 14, as shown in FIG. 1C. In this case, the silicide layer 17a is not formed on the surface of the sidewall spacers 15 and on the HLD layer 16. The silicide layer 17a formed at both sides of the gate electrode 14 is used as source and drain electrodes.
Referring finally to FIG. 1D, the Ti layer 17 where the silicide layer 17a has not been formed is removed to complete the process steps of the conventional meth od for fabricating a semiconductor device.
Since the semiconductor substrate 11 and the gate electrode 14 contain silicon, the silicide layer is formed at interface between the Ti layer 17 and the semiconductor substrate 11 and the gate electrode 14. In contrast, the silicide layer is not formed at other portions.
The above-described conventional method has the following problems.
First, when etching the HLD film, the field oxide layer can be easily damaged. This increases the junction leakage current and affects the device performance.
Second, although the silicide layer is formed after selectively removing the HLD layer, the silicide layer is restrained by O.sub.2 in etching the HLD layer. Thus, the contact resistance and the sheet resistance are increased.
Third, the step coverage between the silicide layer and the HLD layer is very uneven. As a result, planarization becomes inferior throughout the fabrication process.